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Does Substrate Biasing Have a Future?
At Cadence, we often get asked about various low-power design techniques: how well they work, what are the implementation and verification issues associated with them, and how effective they are at...
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Cadence Customers to Showcase Advanced Low-Power Designs at CDNLive!
CDNLive! Silicon Valley, taking place at the DoubleTree Hotel in San Jose, CA next week from March 13-14, 2012, brings together Cadence technology users, developers, and industry experts to network,...
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Assertions Help Avoid Chip Melt
When asked why the use of assertions for low power is rising, I say “at 40nm and below, the chips are just going to melt.” Ann Steffora Mutschler, you quoted me perfectly in your “Avoiding Chip Melt”...
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CDNLive! -- The Other Side of the Low Power Design Techniques
In a recent CDNLive! Silicon Valley presentation titled "Low Power Implementation on the Freescale Kinetis Family," Annis Jarrar from Freescale demonstrated how various low power design techniques were...
View ArticleClik here to view.
Where There's Smoke, There's fire in the Belly of an Aspiring Engineer
Humans learn with their hands and, it turns out, electrical engineers are humans. Most of us fondly recall "experiments" we did that made electrical engineering our destiny. But what of the current...
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Low-Power Design? Brian Bailey Gets It
Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of...
View ArticleClik here to view.
What’s Cool for Low-Power at DAC?
Low-power design promises to be a key theme of the Design Automation Conference once again! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), if you need to cover design,...
View ArticleClik here to view.
Mixed Signals from European Low-Power Designers
Early summer is a good time to visit Europe. I was there for the first couple of weeks in July, before most of Europe disappears on vacation. I spent my time mainly with customers in Germany, Ireland...
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RAK: Conformal Low Power Advanced Features for Power Intent Comparison,...
Why do you define macro models? Luke Lang, Engineering Director at Cadence, says that "Just because you have a hard macro doesn't mean you need to define a macro model: A single-domain hard macro...
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Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year
CDNLive! is back with a bang in 2012, with very strong support from the Cadence user community worldwide. We're three-quarters the way through the events at the time of writing -- you can see the whole...
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Your First Low-power Verification Project - Webinar
So your team just specified its first design with power management circuits. The designers are telling you, its just a few power shut-off domains defined by CPF or UPF. The verification should be...
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Packed House Expected for Cadence Low-Power Technology Summit
It looks like it might be standing room only for latecomers to the Low-Power Technology Summit at Cadence headquarters building 10 auditorium this Thursday (18 October). Registration has been very...
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View ArticleClik here to view.
Assertions Help Avoid Chip Melt
When asked why the use of assertions for low power is rising, I say “at 40nm and below, the chips are just going to melt.” Ann Steffora Mutschler, you quoted me perfectly in your “Avoiding Chip Melt”...
View ArticleClik here to view.
CDNLive! -- The Other Side of the Low Power Design Techniques
In a recent CDNLive! Silicon Valley presentation titled "Low Power Implementation on the Freescale Kinetis Family," Annis Jarrar from Freescale demonstrated how various low power design techniques were...
View ArticleClik here to view.
Where There's Smoke, There's fire in the Belly of an Aspiring Engineer
Humans learn with their hands and, it turns out, electrical engineers are humans. Most of us fondly recall "experiments" we did that made electrical engineering our destiny. But what of the current...
View ArticleClik here to view.
Low-Power Design? Brian Bailey Gets It
Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of...
View ArticleClik here to view.
What’s Cool for Low-Power at DAC?
Low-power design promises to be a key theme of the Design Automation Conference once again! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), if you need to cover design,...
View ArticleClik here to view.
Mixed Signals from European Low-Power Designers
Early summer is a good time to visit Europe. I was there for the first couple of weeks in July, before most of Europe disappears on vacation. I spent my time mainly with customers in Germany, Ireland...
View ArticleClik here to view.
RAK: Conformal Low Power Advanced Features for Power Intent Comparison,...
Why do you define macro models? Luke Lang, Engineering Director at Cadence, says that "Just because you have a hard macro doesn't mean you need to define a macro model: A single-domain hard macro...
View Article
